Two-stage pcm coder with compression characteristic

ABSTRACT

Analog signals within an amplitude range of + OR - 2Uref (Uref being a fixed reference potential) are classified by a decision network as falling within one of 2m positive or negative amplitude bands progressively increasing in width by a factor of 2, the identity of the band being registered by a precoder generating m bits to which is added a further bit indicating the polarity of the signal. An amplitude converter passes each signal to a final coder, with an amplification factor depending upon the particular amplitude band as determined by the decision network. At least a final stage of the amplitude converter works directly into the final coder and includes one or more operational amplifiers each with an additive and a subtractive input, the latter being connected to the amplifier output through a feedback circuit which comprises a voltage divider determining the amplification factor and a source of biasing voltage of magnitude 2Uref for generating a zero output at the lower limit of each band. For the lowest band, ranging between O and Uref/2(2 2), the biasing voltage is cut off. The amplifier output is digitized in the final coder to yield n more bits for a total of 2n m 1 discrete amplitude values.

United States Patent 51 3,688,221

Fruhalf Aug. 29, 1972 [54] TWO-STAGE PCM CODER WITH COMPRESSIONCHARACTERISTIC Waldemar Fruhalf, Berlin, Germany Krone GmbH,Berlin-Zehlendorf, Germany March 2, 1971 Inventor:

Assignee:

Filed:

Appl. No.:

References Cited UNITED STATES PATENTS 3/1965 Miller ..325/38 R X 9/1968Wintringham ..325/38 R X l/l970 Schimpf ..325/38 R X 3/1970 Sekimoto etal. ....325/38 R X Primary Examiner-Alfred L. Brody Att0rneyRoss, KarlF.

[57] ABSTRACT Analog signals within an amplitude range of :ZU (U being afixed reference potential) are classified by a decision network asfalling within one of 2'' positive or negative amplitude bandsprogressively increasing in width by a factor of 2, the identity of theband being registered by a precoder generating m bits to which is addeda further bit indicating the polarity of the signal. An amplitudeconverter passes each signal to a final coder, with an amplificationfactor depending upon the particular amplitude band as determined by thedecision network. At least a final stage of the amplitude converterworks directly into the final coder and includes one or more operationalamplifiers each with an additive and a subtractive input, the latterbeing connected to the amplifier output through a feedback circuit whichcomprises a voltage divider determining the amplification factor and asource of biasing voltage of magnitude 2U for generating a zero outputat the lower limit of each band. For the lowest band, ranging between 0and U /2 the biasing voltage is cut off. The amplifier output isdigitized in the final coder to yield n more bits for a total of 2"""discrete amplitude values;

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II Waldemar FRUHAUF attorney TWO-STAGE PCM CODER WITH COMPRESSIONCIIARACTERISTIC My present invention relates to a pulse-code-modulationsystem of the compander type and, more particularly, to a pulse-codemodulator for such a system having a knee-type compressioncharacteristic to modify the dynamics of a signal voltage to be coded.

Such a compression characteristic consists of 2'" linear segments ofprogressively diminishing slope dividing a range of signal amplitudes,between limits of :U into 2' bands (half of them positive, half of themnegative) whose width increases from the origin outward by a factor of2, except for the two innermost bands on either side of the abscissawhich are of the same width. With the slope of the segments decreasingin the same binary ratio, the output-voltage increment measured by eachsegment along the ordinate has the same constant value AU.

More particularly, and as discussed hereinafter by way of example, sucha characteristic may be divided into 16 segments (eight on each side ofthe origin) so that m 3. If the four innermost segments of identicalslope are considered a single segment, the number of segments reduces to13. Reference may be made in this connection to a CCITT report entitledCOM XV, question No. 33, Temp. Doc. No. 34 of 25 September to 6 October1967.

Thus, the segments of such a characteristic can be defined by a total ofm+l bits, the first bit serving to distinguish between its positive andits negative branches and being therefore necessary only if the signalvoltage to be coded can be of either polarity. Within each segment ofthe characteristic, the amplitude band is further divided into 2"sub-bands represented by n bits so that the sampled signal amplitudeswithin the range can be digitized by an (m+l+ n)-bit code for a total of2"' discrete values. Generally, the value of n equals 4.

Thus, such ananalog signal can be digitized with the aid of two codingstages, i.e. a precoder generating m bits and a final coder generating nbits, with the polarity bit (if any) produced either by a zerocomparator or by the precoder itself. In order to obtain the desiredcompression characteristic, an amplitude converter is used whichintroduces an amplification factor and carries out a subtractiondepending each upon the absolute magnitude of the analog signal to becoded.

In conventional PCM systems of this general type it is customary toplace the amplitude converter ahead of both coding stages whereby theclassification of the signal amplitude, as falling within a particularband, must be carried out by the converter itself. For this purpose theconverter includes a switching matrix controlled by a decision networkwhich discriminates between the various signal amplitudes to select oneof several converter outputs for coding. The decision network,responding to the voltage swing in the converter output, effectivelyforms with the switching matrix a feedback loop which is incapable ofdetecting and correcting a wrong classification once made, due to apossible overshot. As a result, coding errors may persist forconsiderable periods, i.e. until the input signal shifts to a differentamplitude band.

The general object of my present invention is to provide an improvedpulse-code modulator for the type of system referred to which avoids theaforestated drawbacks.

A more particular object is to obviate the need in such a modulator forso-called floating analog switches (which do not respond to a fixedreference potential) as well as constant-current generators, both ofwhich require complex circuitry in order to be realized with thenecessary degree of precision.

It is also an object of my invention to reduce the conventionallyrequired amplification of the input signal which in known systems mustprovide a maximum of 512 V if the final coder operates in a range of 0to 4 V. Such high voltages are difficult to realize in switching cycleson the order of 1 sec as required for the PCM system of the30/32-channel type in which only about 4 ,usec are available for theentire coding process, just a fraction of this time being allotted toamplitude conversion.

These difficulties are overcome, in a system embodying my invention, bythe provision of a precoder which is controlled by the decision networkindependently of the amplitude converter, the latter working directlyinto the final coder while bypassing the precoder. The absolutemagnitude of the output voltage generated by the amplitude converter andfed to the final coder rises linearly from zero within each band, thusenabling the final coder to digitize that output voltage without regardto the location of the band in which it originated.

According to a more specific feature of my invention, the converterincludes differential circuitry for reducing the magnitude of the inputsignal by a threshold value representing the lower limit of therespective band. This differential circuitry may comprise a source ofbiasing voltage for a subtractive (inverting) input terminal of anoperational amplifier forming part of the amplitude converter, the sameinput terminal being connected to a tap on a voltage divider whichextends in a feedback circuit from the amplifier output to a point offixed potential, such as ground. A signal voltage fed to an additiveterminal of this operational amplifier is multiplied by an amplificationfactor which depends on the division ratio of the voltage divider andwhich therefore may be varied by selectively switching some branches ofthe voltage divider into and out of circuit.

As will be shown in detail hereinafter, the switching of one of thesebranches from zero voltage to a biasing voltage of U upon the inputvoltage shifting from the lowest band into a higher one, provides forthe desired constancy of the slope of the compression characteristic inits first two segments if the resistance of this particular branchequals that of a fixed resistor that forms the part of the voltagedivider lying between the output and the inverting input of theoperational amplifier.

Instead of switching a resistance network in the feedback circuit ofsuch an operational amplifier, I may provide a plurality of suchamplifiers with fixed resistors and biasing connections (where needed)in a parallel array to respond to signal amplitudes within respectivebands.

The amplitude converter may also be divided into a first and a secondamplification stage, the first stage including a plurality ofparallel-connected preamplifiers of different amplification ratioswhereas the second stage comprises one or more of the above-describedoperational amplifiers. Selector switches controlled by the decisionnetwork may then be inserted between the two amplification stages forconnecting any one of the preamplifiers in tandem with the operationalamplifier (or one of the operational amplifiers) of the second stage. Asign-responsive detector, generating the polarity bit, may also beinserted between the two amplification stages or may precede theconverter proper; if the converter comprises 2m operational amplifiersconnected in parallel as mentioned above, such a polarity discriminatormay be omitted.

Advantageously, pursuant to another feature of my invention, theamplitude converter and the decision network are fed by an input circuitwhich samples the incoming analog signal and stores it on a capacitor inthe conventional manner but is also provided with an ancillary condenserconnection to neutralize variations in the capacitor charge clue toswitching transients.

The above and other features of my invention will be described in detailhereinafter with reference to the accompanying drawing in which:

FIG. la is a graph of a compression characteristic of the type used in apulse-code modulator embodying my invention;

FIG. lb is a graph showing part of the characteristic of FIG. la on alarger scale together with the corresponding multiplication factors;

FIG. 10 is a similar graph showing the multiplication factors in a firstconverter stage of an embodiment illustrated in FIG. 7;

FIG. Id is a set of graphs showing the digital output of a precoder inthe same embodiment;

FIG. 1e is a graph showing the analog outputs of a first selector in theembodiment of FIG. 7 prior to rectification by an associated inverterstage;

FIG. 1f shows the same analog outputs after rectification;

FIG. lg shows the analog outputs of a second selector cascaded with thefirst one in the same embodiment;

FIG. 1/: is a set of graphs showing the digitized output ofthc finalcoder in that embodiment;

FIG. 2 is a block diagram of a more basic embodiment of my invention;

FIG. 3 is a circuit diagram ofa sampling and holding circuit in theinput of the modulator shown in FIG. 2;

FIG. 4 is a more detailed block diagram of a rectifying stage in theembodiment of FIG. 2;

FIG. 5 is a circuit diagram showing details of a decision network and anassociated precoder included in the system of FIG. 2;

FIG. 6 is a more detailed diagram of an amplitude converter in theembodiment of FIG. 2;

FIG. 7 is a block diagram of another embodiment, referred to inconjunction with FIGS. llc llh;

FIG. 8 is a diagram showing details of a decision network in theembodiment of FIG. 7;

FIG. 9 is a set of graphs showing the quantized output of differentstages of the network of FIG. 8;

FIG. 10 is a circuit diagram of a precoder and control logic included inthe system of FIG. 7;

FIG. 11 is a block diagram similar to FIG. 7, illustrating amodification;

FIG. 12 is a block diagram relating to a further embodiment; and

FIG. 13 is a circuit diagram showing part of a decision network in thesystem of FIG. 12.

In FIG. 1a I have shown a compression characteristic of the typedescribed above, representing the variation of the output voltage U ofan amplitude converter in response to different input voltages U,ranging between a negative limit U,,,.,,, and a positive limit +U,,, ofthe same absolute magnitude. Also indicated in the graph is a referencevoltage U with U 2U The positive branch of the curve, lying in the firstquadrant, and its negative branch, lying in the third quadrant, aremutually symmetrical about the origin 0 and are each subdivided atpoints +0, to +0 and -Q to -Q into 2" linear segments, there being eightsuch segments (m 3) in the example given. The first six segments of thepositive branch have been shown more clearly in FIG. lb; because of thesymmetry, the subsequent discussion will be limited to this positivebranch.

The seven knee point Q Q of the curve are progressively spaced along theabscissa according to a binary law, with the exception of the first twopoints 0,, Q defining bands of like width (equal to U,-,.,/64) for theamplitude of input voltage U,-,,. Thus, the width of the third band(between the points Q and Q is U /3 2, that of the forth band is U /l6,and so forth to a maximum value of U for the eighth band. The slopes ofthe several linear segments defined by these knee points decrease in thesame binary ratio (being identical for the first two segments) so thatthe output voltage U rises from one point to the next by a constantdifferential AU. With the spread AU quantized in 2" steps, as indicatedalong the ordinate in FIG. 1b for n 4, the magnitude of +U,,, may becoded in m-l-n =7 bits. An additional bit, ranking above the others, maybe used to discriminate between positive and negative polarity so thatthe entire range between U,,,,,, and +U,,,,,, can be covered by m+n+l 8bits.

FIG. 11b also shows a series of straight lines k k representing, bytheir slopes, the amplification ratio of an amplitude converteroperating in the range between 0 and U /2, the slopes of these linesbeing related to those of the corresponding curve segments by a suitableproportionality factor p (see FIG. 1c) depending upon the step-down (orpossibly step-up) ratios in other parts of the system. Since only therelative magnitudes of these slopes are significant, their absolutevalue could also be fractional so as to provide amplitude reductionrather than magnification. Again, the first two slopes k and k areidentical as is necessary, because of the logarithmic character of thebinary law, in order to extend the curve to the origin.

The width of each of the first two bands, equaling U, ,,;/64, may alsobe given as U /IZS or, more generally, "max/2 Reference will now be madeto FIG. 2 which shows a pulse-code modulator utilizing an amplitudeconverter with the characteristic just discussed. The system includes aninput stage 1 for the sampling and temporary storage of theinstantaneous amplitude U, of an incoming signal wave W; this stage,described in greater detail hereinafter with reference to FIG. 3, worksinto a zero comparator 2 and in parallel therewith into a rectifyingstage 3, both more completely shown in FIG. 4. Comparator 2 generatesthe first bit to indicate the sign of the instantaneous wave amplitude;it also controls the rectifying stage 3 to invert the stored signalvoltage U, if the same has a specified (e.g. negative) polarity.

The signal voltage U, emerging from rectifier 3 is quantized in adecision network 4 which feeds a precoder 5 to generate a partialthree-bit code identifying one of the eight bands discussed inconnection with FIGS. 1a and lb; the corresponding bits are in second,third and fourth position in the eight-bit code word to be transmittedto a remote station for demodulation by a conventional PCM receiveroperating on an expanding characteristic complementary to that of FIGS.la and lb.

The analog signal from rectifier 3 and the quantized output A fromnetwork 4 are also applied to an amplitude converter 6 which derivestherefrom an output voltage U, within the spread AU for digitization bya final coder 7, of conventional design, generating a partial four-bitcode consisting of the fifth, sixth, seventh and eigth bits of thebinary word. These latter bits thus define one of sixteen steps withinthe band identified by the precoder 5, the spacing of the steps beingrelatively small in the first band and relatively large in the eighthband. This relationship, as is well known, enables message transmissionwith improved signal-to-noise ratio for low-amplitude signals.

FIG. 3 shows an advantageous embodiment of the input stage 1 designedfor rapid sampling and for the suppression of the dynamic zero offsetnormally encountered in such circuits. A storage capacitor C receives acharge of 'either polarity through an operational amplifier 80 havingfixed positive and negative driving voltages (here of :12 V) appliedthereto. Such an amplifier, which may be of the integrated type, has

its output terminal directly connected to its subtractive (i.e.inverting) input terminal by a circuit not shown in FIG. 3 butillustrated in FIG. 4 for a generally similar amplifier 61. If thisamplifier, of gain (1, receives at its additive (or noninverting) inputterminal a voltage V, to be converted into an output voltage V which isfed back to its subtractive input terminal, the two voltages mustsatisfy the equation (V,- V )a= V whence V V a/(1+ a) so that V z V,-for a 1. Thus, the charging amplifier has an amplification factor ofsubstantially unity, along with a very high input impedance and a verylow output impedance.

A generally identical operational amplifier 80' is used to read thecharge of capacitor C,. The charging circuit of this capacitor includesan electronic switch designed as a field-effect transistor 81 whosecontrol gate is connected through a diode 83, shunted by a condenser 84,to the collector of a PNP switching transistor 82 whose base receivessampling pulses SP from a timer 89. With transistor 82 cut off, the gateof PET 81 is strongly negative and the flow of charging current isblocked. In the presence of a sampling pulse SP, transistor 82 conductsand transmits an unblocking pulse to the gate through condenser 84 sothat capacitor C is charged to the new amplitude level of signal voltageU,-. The large voltage jump at the time of switchover is unavoidablytransmitted to capacitor C through the spurious interelectrodecapacitance of the field-effect transistor 81 to as to tend to alter themagnitude of the stored sample. This effect is the more pronounced thesmaller the capacitance C which, on the other hand, should be as low aspossible to facilitate rapid charging inasmuch as the high inputresistance of reading amplifier 80' enables even a small storagecapacitor to hold its charge for the necessary length of time.

In order to compensate for the detrimental effect of the switchingtransients, an ancillary condenser C is inserted between the emitter ofswitching transistor 82 and the capacitor C this emitter being connectedto its source of operating voltage (here of +6 V as against a collectorvoltage of -12 V and a base voltage of +12 V) through a biasing resistor85 which causes the transistor 82 to operate as an emitter-follower infeeding a balancing pulse to capacitor C through the advantageouslyadjustable condenser C With proper adjustment of this condenser, theeffect of the sampling pulse upon the magnitude of the stored charge canbe neutralized.

FIG. 4 shows the zero comparator or polarity detector 2 together withthe rectifying stage 3, the components being advantageously combintedinto an integrated module. Comparator 2 comprises a differentialamplifier with an additive input at ground potential and a subtractiveinput receiving the stored signal voltage U from the output ofsampler 1. The same signal voltage is fed via a resistor 63 to thesubtractive input of the aforementioned operational amplifier 61 which,in the manner described with reference to amplifiers 80 and 80' of FIG.3, has a fixed resistor 65 inserted between that input and its output.The additive input of amplifier 61, which forms part of the rectifier 3,is grounded through a resistor 64. Since, as discussed above, such anoperational amplifier generates an output voltage substantially equal tothe potential difference between its additive and subtractive inputterminals, the application of signal voltage to its subtractive inputcauses the amplifier input 61 to act as an inverter. Amplifier 60, whichis of the unipolar type, has no output in the presence of a positiveinput signal but works into a negator N having a true output under theseconditions. Two switches S and S are located in the direct path ofsignal U, and in its inverted path, i.e. in the output of amplifier 61,respectively; switch S is controlled by the direct output of amplifier60 whereas switch S responds to the output of negator N so that thesetwo switches are alternately opened and closed. In the specific caseassumed, each switch makes when its controlling voltage is zero andbreaks when that voltage assumes a finite value; a positive signalvoltage U, is therefore passed by the switch S directly to a furtheramplifier 62, acting as an impedance transformer, whereas a negativesignal voltage is inverted in amplifier 61 and fed to amplifier 62 byway of switch S The two switches advantageously are constituted bybidirectional electronic devices such as the field-effect transistor 81of FIG. 3; the same applies to 'other switches described hereinafter andrepresented diagrammatically as pairs of contacts.

Details of the decision network 4, the precoder Sand the amplitudeconverter 6 are shown in FIG. 5. Network 4 comprises seven quantizingstages in the form of respective comparators 71 77 each similar to thedifferential amplifier 60 of FIG. 4, their additive inputs (i-) beingmultipled to a bus bar carrying the input voltage U, (from the output ofthe amplifier 62, FIG. 4) while their subtractive inputs are tied todifferent taps on a voltage divider of overall resistance r connectedbetween ground and a conductor 87 of potential U This voltage dividerconsists of a series of resistors 80 86 so proportioned that successivechain, have potentials equaling consecutive binary fractions of U Thus,the respective magnitudes of resistors W as are r/2, r/4, r/8, r/l6,r/32, r/64 and r/64. With conductor 87 connected directly to thesubtractive input of conparator '77, the junction of resistors 80 andfill (potential U /2) is tied to the corresponding input of comparator76, that of resistors 81 and 82 (potential U /4) isjoined to a likeinput of comparator 75, and so forth, the threshold voltage applied tothe subtractive input of the last comparator Til by the junction ofresistors $5 and 86 being equal to U /64. Input voltage U,,, on bus barm is therefore quantized, with one or more comparators 71-77 conductingwhenever that voltage exceeds the first threshold U /64.

Amplitude discriminators 71 7'7 work into respective negators (N, Nwhose true outputs, if present, bias respective NPN transistors T, Tinto saturation, i.e. a stage in which the effective resistance of eachof these transistors drops to a negligible value of about 1 ohm.Transistors T, T, have their emitters grounded and have their collectorsconnected through respective resistors R, R to a bus bar 88 terminatingat the subtractive input terminal of another operational amplifier 9t)which will be described in greater detail with reference to FIG. 6 andis similar to amplifier oil of FIG. 4i. The additive input terminal ofamplifier 9i) is connected to bus bar 70 to receive the analog voltageU,-,, therefrom. If this analog voltage is below the first threshold U/64, all the negators N, N, conduct and all the NPN transistors T, T,are saturated; a further transistor T of PNP type, is connected betweenresistor R, and a source of biasing voltage equal to +2U,.,,, transistorT being cut off under these conditions. As soon as voltage U,-,, risesinto or beyond its second am plitude band, comparator ill responds sothat negator N, cuts off the transistor T, and turns on the transistor Twhich, saturating, switches the resistor R, from ground potential tobiasing potential +2U, The other resistors R R,, normally groundedthrough their respective NPN transistors, are simply opemcircuited bythe response of the corresponding comparators 7'11 77.

The comparators and the associated negators, whose respective outputshave been designated A, A, and A, A constitute the decision network 4whereas the transistors T T, and the operational amplifier 90 form partof the amplitude converter 6. The precoder 5, also shown in FIG. 5,includes a number of NAND gates 61-0; gates and (is (illustrated in theequivalent from of OR gates with inverting inputs) generate the thirdand fourth bits, respectively, while the second bit is directly obtainedfrom the output A, of comparator 7 :1. NAND gate (3,, working into oneinput of gate 6,, receives the outputs A, and A, of comparator '72 andnetwork N,; the other input of gate G is directly energized from theoutput A, of negator N Gate 6,, has a first input receiving the outputA, of negator N a second input fed from gate G which in turn isenergized from outputs A, and A, of comparator '75 and negator N,,, athird input supplied by the gate G to which the outputs A and A, f omprator 3 an negator N, are delivered, and a fourth input tied to theoutput of gate G, which in turn derives its inputs from outputs A, andA, of comparator 7i and negator N The logic of FIG. g corresponds to thefollowing Boolean equations for the three bits generated by the precoder5:

bit No. 2 A,

FIG. 6 shows the operational amplifier 90 of FIG. 5 together with itsbiasing resistors R,, and R, R,, the transistors T T, of FIG. 5 havingbeen diagrammatically represented in FIG. it by switches Sw, Sw, (withreversing switch Sw, replacing the two transistors T,,, T, of oppositeconductivity type). Resistors R, R,, collectively designated R,,, formwith resistor R,, a voltage divider having a tap P connected to thesubtractive input terminal of the amplifier. Normally, i.e. with zeroinput voltage U,,,, switch Sw, is on its grounded contact (correspondingto saturation of transistor T, in FIG. 5) while the six other switchesare closed.

Disregarding for the present the biasing voltage U B +2U,.,, we canestablish the following relationship between input voltage U,,,, outputvoltage U and feedback voltage U (at point P):

out a UM: (UV Up) a: m-

whence out III

R, bear the following binary relationship with the fixed resistance R,,:

The largest of these resistors, R,, has the least electrical weightbecause of its connection in parallel with the others.

The magnitude of resistance R is given by l 1 F 3?, where R, designatesany of the weighting resistors R, R effectively connected in circuit.For low input voltages U,-,,, i.e. with all switches Sw, Sw, in theirillustrated positions, R, R,,/127 corresponding to an amplificationfactor k 128 2 Let us now consider the case of an input voltage fallingwithin the second-lowest band, i.e. ranging between U /64 and U /BZ.Switch SW, is now reversed so that biasing voltage U +2U,- is connectedthrough weighting resistor R, to the tap P of the voltage divider, i.e.to the subtractive input of amplifier 90. Under these conditions themagnitude of feedback potential U is given by the relationship Q9ILLwhence out iu ref The magnitude of R, has now been changed to R /l27 sothat, within the amplitude band considered, U 128U,, ZU For the lowerlimit of the second band, i.e. for U, U /64, this corresponds exactly toU O. The slope of the linear function U =f(U,,,) within the second bandis identical with that in the first band, i.e. k= 128.

In the third band, with switch SW2 open to disconnect resistance branchR R, R /63. Thus, we now have U 64U ZU this function being again astraight line starting with U 0 at the lower bandlimit of U U,,,,/ 32.The slope is now half that of the previous two functions, i.e. k 64.Thus, the function U =f(U;,,) corresponds precisely to the straightlines k, k etc. illustrated in FIG. 1b. In the highest band, with allswitches SW2 Sw, open, R as so that U 2(U, U,,.,); the amplificationfactor is now 2.

According to FIG. 7, in which elements having counterparts in theforegoing Figures have been designated by the same reference numeralspreceded by a lin the position of the hundreds digit, the amplitudeconverter 6 of the aforedescribed embodiment has been split into twostages 106' and 106" forming part of a precoding module 100' and afinal-coding module 100", respectively. Converter stage 106' comprisesthree operational amplifiers 143, 144 and 145 which take the place ofcharging amplifier 80, FIG. 3, and are connected in parallel to a commoninput carrying the signal voltage U these three amplifiers havingrespective amplification factors k l, k 4 and k 16.

' Module 100' further includes a sampler 101, with three sections 146,147 and 148 respectively energized by amplifiers 143, 144 and 145, adecision network 104 with three inputs receiving the output voltages U Uand U of sampler sections 146 148, and a precoder modified by thecompression characteristic. An extension 105" of precoder 105, shown forconvenience as included within module 100", represents a logic networkfor the control of a first selector 112, inserted between converterstages 106' and 106", an inverter stage 103 for changing the outputvoltage U of this selector (FIG. 1e) into a rectified voltage U (FIG.1]), a second selector 117 following the converter stage 106" to delivera voltage U,,"(FIG. lg) of maximum amplitude AU, and a final coder 107which generates the fifth, sixth, seventh and eighth bits. Converterstage 106" includes three operational amplifiers 114, 115 and 116, eachof the type described in conjunction with FIG. 6, whose feedbackresistances are selected to give them amplification factors k 8(amplifier 114), k 4 (amplifier 115) and k 2 (amplifier 116). Theseveral outputs of control logic 105", shown in greater detail in FIG.10, have been diagrammatically illustrated in FIG. 7 as single linesincluding a line ES terminating at selector 112, a line GL leading torectifier 103, a line KV controlling the selector 117, and a furtherline KV terminating at amplifier 114 for the purpose of selectivelyswitching one of its weighting resistances between ground and a fixedbiasing voltage of magnitude 2U as described above in connection withresistor R ofFIG. 6.

The various amplification factors of amplifiers 143 145 and 114 116enable the selective establishment of the same seven differentamplification ratios as in the preceding embodiment, ranging between128:] and 2:1, by connecting different combinations of these amplifiersin tandem through the closure of appropriately chosen switchcombinations in selectors 112 and 117. Thus, closure of the lowestswitch of selector 112 gives an overall ratio of 128:1, 64:1 or 32:1, asrequired for the four lowest amplitude bands, according to whether theupper, the middle or the lower switch of selector 117 conducts. With themiddle switch of selector 112 conducting, closure of either the middleswitch or the lower switch of selector 117 yields the ratios 16:1 and8:1 needed for the next two bands. Upon the closing of the top switch ofselector 1 12, corresponding to anamplification factor of unity in thefirst converter stage 106', an overall ratio of 4:1 or 2:1 can beestablished by closing either the middle switch or the bottomswitch ofselector 117. The logic circuit for carrying out these selectiveswitching operations, under the control the quantized output of network104, is described herei aheryti etsrenqe EEG-19;. a

As shown in FIG. 8, thedecision network 104 inas passed by the amplifier134 of FIG. 7 (k l) and sampled in section 146 of storage unit 101. Thisvoltage is applied to the additive input of one comparator and to thesubtractive input of the other comparator of each pair 136, 137 whoseremaining inputs are biased with voltages equal to iU IZ and iUrespectively. Comparators 134 and 135 operate on input voltage U, 4U thebiasing voltages being the same as for comparators 136 and 137,respectively. Comparators 131, 1.32 and 133 are energized by inputvoltage U, 4U l6U which is being matched against respective biasingvoltages iU /4, iU l2 and :U,,,,. The resulting binary outputs have beenillustrated in graphs (a) (h) Qf G-.9-

As shown in graph (a), the output A is false (i.e. has

the logical value O) forall negative voltages U,-,, and is true (i.e.has the logical value I) for all positive input voltages. Graph (b)shows the output A to be true everywhere except within the region fromU,,.,/ 64 to +U /64. Output A graph (c), is false within the region fromU, ,/32 to +U /32, as shown. The corresponding region for output A graph(d), extends from U,. ,/8 to +U /8. According to graphs (j), (g) and(h), the outputs A A and A are suppressed within limits iU /4, i U IZand iU respectively.

FIG. 10 shows the amplification factors of the three operationalamplifiers 143, 144 and 145 as manifested in the outputs U U and U ofcorresponding sampling sections 146, 147 and 148. The horizontal linesat the top and the bottom of this graph indicate the saturation ofamplifiers 146 and 147 at the limits of their linear operating ranges.These operating ranges correspond in FIG. 1a to the curve portionbounded by .PQ UQJTQL and +124. r. pl fierlfiilhsa t pn...

bounded by points Q and +0 for amplifier 147, and

the complete range between end points Q and +08 for amplifier 148.

FIG. III shows a logic circuit W5 which combines both the precoderlltle" and the controller MP5" of FIG. '7. This circuit has eight inputsE B, respectively tied to the outputs A A of FIG. Input E is connectedthrough two cascaded negators N and N to a lead GL- which, together witha lead GL+ extending from the output of negator N constitutes the lineGL shown in FIG. 7. Lead GL- carries the first (sign) bit and controlsthe switch S (cf. FIG. 4) of rectifier W3 which is identical with'theinverting stage 3 of the first embodiment; its companion switch S iscontrolled by lead GL+. It is recalled that these switches,advantageously constituted by field-effect transistors as already noted,are open in the energized state and closed in the deenergized state oftheir respective control leads. Thus, the presence of a true input E(indicative of a positive input voltage U cuts off the negator N toclose the switch S while negator N, conducts to open the switch 52.

Input E, is connected through a negator N to the lead liV which controlsthe amplifier M4 (FIG. '7) to switch one of its weighting resistancesfrom ground to biasing voltage U (cf, FIG. 6) whenever the input voltageU, rises above the lowest threshold U 64, in the manner and for thereason already explained. The output of negator N is delivered through afurther negator N, to an input of a NAND gate G having its other inputconnected through another negator N, to network input E2. Negatgr N4works through a negator N into a lead KV which, together with twofurther leads KV and I(V forms part of the line designated IIV in FIG. 7and controlling the selector 1117. Lead I(V energized in the presence ofa true input E opens the top switch of selector lll'7 to deactivate theoperational amplifier I14, of amplification ratio k 8, whenever theamplitude of the signal U rises above the second step equal to U fighlegator ll;, also works into an Ahllj gate G generating the controlsignal on lead lKV for the middle switch of selector ll7; also connectedqt e om uts onesator this an input of a NAND gate G whose other inputreceives the signal on network input E, through a negator big. Theoutput of the latter negator is fed to a NAND gate G also receiving thesignal on input E and in parallel therewith through a negator hi to alead BS which with two similar leads E8 E5 forms part of the line ESshown in FIG. '7. Lead E8 which carries the second bit, controls the topswitch of selector M2 to open it whenever that bit has the logical valuell, i.e. in the presence of a true input E4. Input E5 terminates at aNAND gate G also receiving the signal of input Er, through a negator Nthe latter feeding respective inputs of two NAND gates G15, G11 as wellas aNAND gate G feeding the lead ES which controls the bottom switch ofselector M2 to close it in the presence of a true input E Gate Ggenerates the third bit of the code word. Gate G whose other input isconnected to lead E5 works into lead ES, which controls the middleswitch of selector Ill2, closing it upon the simultaneous presence of aninput E, and absence of an input E Input E, is connected through anegator N, to one input of a NAND gate G8 whose other two inputs receivethe outputs of NAND gates G12 and G gate G8 works through a negator Ninto lead KV, which controls the bottom switch of selector lll'7,closing it whenever the signal amplitude reaches the 4th, 6th or 3thband. Negator N8 and NAND gates G", G and GM are also connected torespective inputs of a NAND gate 6:, producing the fourth bit. A secondinput of the gate G10 is excited through a negator N from the output ofthe gate G9. Thus, the middle switch of selector 1117 is closed wheneverthe signal amplitude reaches the third, fifth or seventh band. w

The following Boolean equations apply to the generation of bits Nos. 1 4as well as to the energization of leads KV liV ES, E8 and GL+, GL by thelogic of FIG. III in the response to different combinations of outputs AA of network I04;

second bit =A2 third bit=A2- 5 A.

live A1 With this mode of operation, selector ll2 completes the outputcircuit of amplifier 145 (lead E8 de-ener gized) as long as comparator134 in FIG. 8 has no output, i.e. with the input voltage remainingbeneath the threshold U /8 of the fifth band (point Q. in FIG. lb). Inthe next two bands, i.e. up to point Q6, selector 112 renders theamplifier Md effective (de-energization of lead E8 For all higher inputvoltages, amplifier 143 is operative (zero voltage on lead E5 This hasbeen graphically illustrated in FIG. le which shows the output voltageU, of selector ll2 plotted against the input voltage U, of converterstage I06. Following rectification in inverter stage M3, this outputvoltage has the form U as shown in FIG. lf. Finally, the secondconverter stage W6" produces, together with selector 117, the outputvoltage U," shown in FIG. lg, this voltage being suitable fordigitization by the final coder 107 whose output is illustrated in FIG.1 h.

From FIGS. Id and lh it will be apparent that any of bits Nos. 3 8,generated partly by precoder and partly by final coder lIl'l, mayrepresent the different spreads of analog values in accordance with thecompression characteristic of FIG. la. For the lowest amplitude bandsthe sixth, seventh and eighth bits had to be omitted in FIG. lb becauseof insufficient resolution.

Since the decision network 104 is connected to the output of sampler lblahead of the first selector I12, the position of that selector has noinfluence upon the quantizing operation of that network. On the otherhand, the preamplification of the lower signal voltages by converterstage I06 greatly reduces the relative noise level in the input of thedecision network so as to minimize operational errors.

FIG. ll shows a somewhat simplified system of the same general characteras that of FIG. 7, i.e. with a preamplification stage 2% ahead of asampler 201 and a second converter stage 2%" directly working into afinal coder 207. Converter stage 206' comprises only two parallelamplifiers 243 and 245 of amplification factor k =1 and k l6respectively, their outputs being chopped by associated sections 246 and248 of sampler 201. A rectification stage 203 beyond sampler 201 includes two inverters 250 and 251; a decision network 204 receives theoutputs of sampling sections 246, 248 directly over leads 252, 253 andvia inverters 250, 251 over leads 254, 255. Leads 252 255 are alsoconnected to a single selector 212 which is controlled from a logiccircuit 205 via a line ES and connects any one of these leads to theinput of converter stage 206" comprising a single operational amplifierof the type described in connection with FIG. 6. A lead KV' extendingfrom logic circuit 205 to amplifier 206" again serves to switch a leastsignificant weighting resistance between ground and a fixed biasingpotential, as described above, upon the input signal surpassing thefirst amplitude band as determined by the network 204 and reported tocircuit 205 which also contains the precoder generating the first fourbits. The final coder 207 produces bits Nos. 8 as in the precedingembodiment.

Network 204 receives voltages of only one polarity (assumed to bepositive) from rectifier stage 203 so that its comparison matrix,generally similar to that shown in FIG. 8, can be simplified byreplacing each dual comparator thereof with a single comparator.Depending on the origin of the signal, i.e. whether from a noninvertinglead 252, 253 or an inverting lead 254, 255, a zero comparator similarto unit 130 and connected to, say, lead 253 from high-amplification unit248 determines the character of the first bit emitted by logic 205 toindicate the polarity of the input signal. A first group of comparatorsin network 204, receiving the amplified voltage sample from section 248via leads 253 and 255 over a common OR gate, compares that voltagesample with three different thresholds +U,-,.,/4, +U, /2 and +U in themanner shown fan the right: hand halves "of comparators 131,132 and 133in FIG. 8 to generate the outputs A, A, discussed above; a second groupof comparators, similarly energized from leads 252 and 254 through acommon OR gate, makes the comparison with thresholds +U, ,,,/8,+U,-,.,/4, +U,.,.,/ 2 and +U,-,, to generate outputs A, A,. The logic205 is generally similar to that of FIG. 10 except that the output A, ofthe zero comparator must be taken into account in determining which ofthe four switches of selector 212 is to be closed in response to a givenamplitude and polarity of the input signal.

Since in FIG. 11 the voltages to be analyzed have all the same polarity,the electronic switches of selector 212 may be simpler than those of theselector 112 in FIG. 7.

In the system of FIG. 12 and 13 I have gone one step beyond theembodiments of FIGS. 7 11 by relocating all the operational amplifiersof the amplitude converter into the preamplification stage which hasbeen designated 306' in FIG. 12, the final converter stage 306" beingconstituted in this case simply by a selector switch 312. Converterstage 306 comprises 16 amplifiers 390 397 and 390" 397", each similar tothe amplifier 90 of FIG. 6, having their additive inputs connected inparallel to a common terminal 399 which receives the input signal to beanalyzed. A sampler, not shown in FIG. 12, may precede the amplificationstage 306' even though it is also possible to insert an individualsampling section in the output of each amplifier in the manner shown inFIG. 7. Since integrated operational amplifiers are commerciallyavailable at relatively low cost, the use of a multiplicity of suchamplifiers does not create a major economic problem.

Each of these amplifiers is assigned to a respective amplitude band inthe first quadrant (units 390 397) or in the third quadrant (units 390"397") in which its operation is linear. Amplifiers 390' and 390"operating on the lowest positive and negative band, respectively, havefixed weighting resistors R, and R," whosemagnitudes correspond to thatof the resistance network R, R, in FIG. 6 with all branches grounded.

The next two amplifiers in the array, i.e. unit 391 on the positive and391" on the negative side, have their subtractive inputs connected torespective sources of positive and negative biasing voltage +2U and2U,.,.,

by way of series resistors R, and R, equivalent to recreases to infinityfor the outermost amplifiers 39? and V 397", i.e. to a conditioncorresponding to the opening of all switches Sw, Sw, in FIG. 6.

Thus, the sixteen amplifiers of FIG. 12 generate output voltages U U,and U U," which are fed to a decision network 304 ahead of selector 312.Network 304 controls a precoder 305 which generates bits Nos. 1 4, as inthe system of FIG. 7, and also operates the 16 switches X X, and X X,"of selector 312 feeding a final coder 307 for the generation of the lastfour bits.

Network 304 may include a multiplicity of coincidence gates forselectively passing the output of only the one amplifier which operatesin its linear range, one group of these gates being provided for thepositive voltages detected by amplifiers 390' 397' while an identicalsecond group operates on the outputs of the negative-voltage detectors390" 397". FIG. 13 shows the first group of AND gates, designated Y Ywhose outputs control the switches X X, whereas switch X, is directlycontrolled by the output lead U, of amplifier 397'. Each of these gateshas a single noninverting input for the associated amplifier output andone or more inverting inputs receiving the outputs of all higher-orderamplifiers of the series, i.e. of amplifier 397' in the case of gateY,,, of amplifiers 397 and 396 in the case of gateYs, and so forth;between each amplifier 390' 397' and the associated gate Y Y, arespective comparator 400 407 is inserted for converting the analogsignals U U into digital signals which can be processed by the gates Y YBy this lockout circuit the conduction of any amplifier other than unit390 or 390 cuts off all the lower-ranking amplifiers on thecorresponding (positive or negative) side of the system so that only oneof the switches of selector 312 is closed at any time.

It will be apparent that the system of FIGS. 12 and 13 could be modifiedby placing a zero comparator and rectifying stage as shown in FIG. 4ahead-of the converter stage 306', with a halving of the number ofamplifiers and generation of the first bit in the zero comparator ratherthan in the precoder 305.

it is evident that the number of bits produced by both the precoder andthe final coder may be varied, the high degree of sensitivity of myimproved system (particularly when using preamplification) enabling thesubdivision of each band into more than sixteen amplitude steps to bedigitized in, for example, six bits of a -bit code word.

lclaim:

l. A pulse-code modulator for signal voltages within a predeterminedamplitude range divided into at least 2' bands of a width increasingaccording to a binary law, comprising:

input means for the temporary storage of a signal voltage to be coded;

a decision network connected to receive such signal voltage from saidinput means for ascertaining the band into which its amplitude falls;

an amplitude converter connected to said input means and controlled bysaid decision network for multiplying the magnitude of said signalvoltage by a factor varying with the location of said band within saidrange and provided with differential circuitry for reducing themagnitude of said signal voltage by a threshold value representing thelower limit of the respective band, with generation of an output voltagerising linearly from zero within each band;

a precoder controlled by said decision network independently of saidconverter for identifying the band thus ascertained and translating theidentity thereof into a first partial code of m bits;

and a final coder directly connected to said converter for translatingsaid output voltage into a second partial code of bits.

2. A modulator as defined in claim ll wherein said converter comprisesoperational amplifier means with an additive input terminal, asubtractive input terminal and an output terminal, a voltage dividerconnected between said output terminal and a point of fixed potential,and a feedback connection from a tap on said voltage divider to saidsubtractive input terminal, said differential circuitry including asource of biasing voltage for said subtractive input terminal.

3. A modulator as defined in claim 2 wherein said voltage dividerincludes a fixed resistor between said output and subtractive inputterminals and variable-resistance means between said subtractive inputand said point of fixed potential, said circuitry comprising switchmeans controlled by said decision network for alternately connecting apart of said variable-resistance means to said point of fixed potentialand to said source of biasing voltage.

ll. A modulator as defined in claim 3 wherein said part of saidvariable-resistance means and said fixed resistors have equalresistance.

5. A modulator as defined in claim 4 wherein said range has an upperlimit equaling the value of said biasing voltage, saidvariable-resistance means comprising 2'"-1 parallel resistive brancheswith resistances of R /Z where i is an integer ranging from 0 to m, Rbeing the resistance of said fixed resistor, said part of saidvariable-resistance means being the electrically least significant oneof said branches, said converter further including individual switchesin said branches controlled by said decision network, said fixedpotential being zero volts.

6. A modulator as defined in claim 5 wherein said decision networkcomprises 2"1 comparators for matching said signal voltage withrespective binary fractions U /Z of said biasing voltage U and foropen-circuiting any of said branches, other than the least significantbranch of magnitude R upon said signal voltage reaching the level of thecorresponding binary fraction of said biasing voltage, said switch meansbeing operable by one of said comparators to switch said branch ofmagnitude R from zero volts to said biasing voltage ZU upon said signalvoltage reaching the lowest fraction equal to U,,,,, 2"1

l. A modulator as defined in claim 6 wherein said switch means comprisesa pair of transistors of opposite conductivity type alternatelysaturable by said one of said comparators.

8. A modulator as defined in claim 2 wherein said operational amplifiermeans comprises at least 2 amplifier units connected in parallel to saidinput means and biased to cut off at the lower limits of respectivebands, said decision network being a logic matrix with input connectionsto the output terminals of said amplifier units, said converter furtherincluding a set of switches controlled by said logic matrix forselectively connecting said output terminals to said final coder.

9. A modulator as defined in claim 2 wherein said converter includes afirst amplification stage with a plurality of parallel-connectedamplifiers of different amplification ratio, a second amplificationstage comprising said operational amplifier means, and switch meansbetween said stages for selectively connecting any one of saidparallel-connected amplifiers in tandem with said operational amplifiermeans under the control of said decision network, the latter havinginput connections energizable by said first amplification stage.

it). A modulator as defined in claim 9 wherein said converter furtherincludes polarity-inverting means between said amplification stages,said decision network comprising sign-responsive detector meanscontrolling said polarity-inverting means.

iii. A modulator as defined in claim 9 wherein said input meanscomprises a plurality of sampling circuits inserted between said firstamplification stage and said switch means, each of said samplingcircuits including a storage capacitor connectable by said switch meansto said second amplification stage.

12. A modulator as defined in claim 2 wherein said converter furtherincludes polarity-inverting means ahead of said operational amplifiermeans and signresponsive detector means connected to said input meansahead of said polarity-inverting means for controlling the latter.

13. A modulator as defined in claim 1 wherein said input means comprisesa sampling circuit with a storage capacitor, electronic switch means ina charging path for said capacitor, and ancillary condenser meansconnected between said switch means and said capacitor for compensatingvariations in the charge thereof due to switching transients.

M. A modulator as defined in claim 13 wherein said electronic switchmeans comprises a switching transistor responsive to timing pulses and afield-effect transistor in series with said capacitor, said switchingtransistor having a collector coupled to a gate electrode of saidfield-efiect transistor and further having an emitter biased through aresistance and connected to

1. A pulse-code modulator for signal voltages within a predeterminedamplitude range divided into at least 2m bands of a width increasingaccording to a binary law, comprising: input means for the temporarystorage of a signal voltage to be coded; a decision network connected toreceive such signal voltage from said input means for ascertaining theband into whiCh its amplitude falls; an amplitude converter connected tosaid input means and controlled by said decision network for multiplyingthe magnitude of said signal voltage by a factor varying with thelocation of said band within said range and provided with differentialcircuitry for reducing the magnitude of said signal voltage by athreshold value representing the lower limit of the respective band,with generation of an output voltage rising linearly from zero withineach band; a precoder controlled by said decision network independentlyof said converter for identifying the band thus ascertained andtranslating the identity thereof into a first partial code of m bits;and a final coder directly connected to said converter for translatingsaid output voltage into a second partial code of n bits.
 2. A modulatoras defined in claim 1 wherein said converter comprises operationalamplifier means with an additive input terminal, a subtractive inputterminal and an output terminal, a voltage divider connected betweensaid output terminal and a point of fixed potential, and a feedbackconnection from a tap on said voltage divider to said subtractive inputterminal, said differential circuitry including a source of biasingvoltage for said subtractive input terminal.
 3. A modulator as definedin claim 2 wherein said voltage divider includes a fixed resistorbetween said output and subtractive input terminals andvariable-resistance means between said subtractive input and said pointof fixed potential, said circuitry comprising switch means controlled bysaid decision network for alternately connecting a part of saidvariable-resistance means to said point of fixed potential and to saidsource of biasing voltage.
 4. A modulator as defined in claim 3 whereinsaid part of said variable-resistance means and said fixed resistorshave equal resistance.
 5. A modulator as defined in claim 4 wherein saidrange has an upper limit equaling the value of said biasing voltage,said variable-resistance means comprising 2m-1 parallel resistivebranches with resistances of R0/2i where i is an integer ranging from 0to m, R0 being the resistance of said fixed resistor, said part of saidvariable-resistance means being the electrically least significant oneof said branches, said converter further including individual switchesin said branches controlled by said decision network, said fixedpotential being zero volts.
 6. A modulator as defined in claim 5 whereinsaid decision network comprises 2m-1 comparators for matching saidsignal voltage with respective binary fractions Umax/2k of said biasingvoltage Umax and for open-circuiting any of said branches, other thanthe least significant branch of magnitude R0, upon said signal voltagereaching the level of the corresponding binary fraction of said biasingvoltage, said switch means being operable by one of said comparators toswitch said branch of magnitude R0 from zero volts to said biasingvoltage 2Uref upon said signal voltage reaching the lowest fractionequal to Umax/(2m-1).
 7. A modulator as defined in claim 6 wherein saidswitch means comprises a pair of transistors of opposite conductivitytype alternately saturable by said one of said comparators.
 8. Amodulator as defined in claim 2 wherein said operational amplifier meanscomprises at least 2m amplifier units connected in parallel to saidinput means and biased to cut off at the lower limits of respectivebands, said decision network being a logic matrix with input connectionsto the output terminals of said amplifier units, said converter furtherincluding a set of switches controlled by said logic matrix forselectively connecting said output terminals to said final coder.
 9. Amodulator as defined in claim 2 wherein said converter includes a firstamplificatiOn stage with a plurality of parallel-connected amplifiers ofdifferent amplification ratio, a second amplification stage comprisingsaid operational amplifier means, and switch means between said stagesfor selectively connecting any one of said parallel-connected amplifiersin tandem with said operational amplifier means under the control ofsaid decision network, the latter having input connections energizableby said first amplification stage.
 10. A modulator as defined in claim 9wherein said converter further includes polarity-inverting means betweensaid amplification stages, said decision network comprisingsign-responsive detector means controlling said polarity-invertingmeans.
 11. A modulator as defined in claim 9 wherein said input meanscomprises a plurality of sampling circuits inserted between said firstamplification stage and said switch means, each of said samplingcircuits including a storage capacitor connectable by said switch meansto said second amplification stage.
 12. A modulator as defined in claim2 wherein said converter further includes polarity-inverting means aheadof said operational amplifier means and sign-responsive detector meansconnected to said input means ahead of said polarity-inverting means forcontrolling the latter.
 13. A modulator as defined in claim 1 whereinsaid input means comprises a sampling circuit with a storage capacitor,electronic switch means in a charging path for said capacitor, andancillary condenser means connected between said switch means and saidcapacitor for compensating variations in the charge thereof due toswitching transients.
 14. A modulator as defined in claim 13 whereinsaid electronic switch means comprises a switching transistor responsiveto timing pulses and a field-effect transistor in series with saidcapacitor, said switching transistor having a collector coupled to agate electrode of said field-effect transistor and further having anemitter biased through a resistance and connected to said capacitor byway of said ancillary condenser means.